ARM ARM7TDMI - Figure 3-12 Bidirectional Bus Timing; Figure 3-13 Unidirectional Bus Timing

Memory Interface
3-18 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Figure 3-12 Bidirectional bus timing
Unidirectional data bus
When BUSEN is HIGH, all instructions and input data are presented on the input data
bus, DIN[31:0]. The timing of this data is similar to that of the bidirectional bus when
in input mode. Data must be set up and held to the falling edge of MCLK. For the exact
timing requirements see Chapter 7 AC and DC Parameters.
In this configuration, all output data is presented on DOUT[31:0]. The value on this bus
only changes when the processor performs a store cycle. Again, the timing of the data
is similar to that of the bidirectional data bus. The value on DOUT[31:0] changes after
the falling edge of MCLK.
The bus timing of a read-write-read cycle combination is shown in Figure 3-13.
Figure 3-13 Unidirectional bus timing
When the unidirectional data buses are being used, and BUSEN is HIGH, the
bidirectional bus, D[31:0], must be left unconnected.
The unidirectional buses are typically used internally in ASIC embedded applications.
Externally, most systems still require a bidirectional data bus to interface to external
memory. Figure 3-14 on page 3-19 shows how you can join the unidirectional buses up
at the pads of an ASIC to connect to an external bidirectional bus.
MCLK
D[31:0]
read cycle write cycle read cycle
D1
Dout
D2
D1 Dout
read cycle write cycle
read cycle
D2
MCLK
DIN[31:0]
DOUT[31:0]
D[31:0]