ARM ARM7TDMI - Figure B-1 ARM7 TDMI Core Scan Chain Arrangements

Debug in Depth
B-4 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Figure B-1 ARM7TDMI core scan chain arrangements
Scan chain 0
Scan chain 0 enables access to the entire periphery of the ARM7TDMI core, including
the data bus. The scan chain functions enable inter-device testing (EXTEST) and serial
testing of the core (INTEST). The order of the scan chain, from search data in to out, is:
1. Data bus bits 0 to 31.
2. The core control signals.
3. Address bus bits 31 to 0.
4. EmbeddedICE-RT control signals.
The EmbeddedICE-RT control signals (specifically DBGRQI) are scanned out
first.
Scan chain 1
Scan chain 1 is a subset of scan chain 0 and BREAKPT. It provides serial access to the
core data bus D[31:0] and the BREAKPT signal.
There are 33 bits in this scan chain, the order from serial data in to serial data out, is:
1. Data bus bits 0 to 31.
2. The BREAKPT bit, the first to be shifted out.
ARM CPU
main processor
logic
EmbeddedICE-RT
logic
TAP controller
Scan chain 2
Scan chain 0
Scan chain 1
BREAKPT
ARM7TDMI processor