Debug in Depth
B-52 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
B.15.1 Disabling EmbeddedICE-RT
The breakpoint and watchpoint registers are programmed from the JTAG port at the rate
of TCK, but the core is synchronized to MCLK. MCLK and TCK are asynchronous,
so disabling EICE-RT (by setting bit [5]) prevents metastable signals from entering the
core.
Whenever the setting of bit [5] is changed, it must be read back again and polled until
the new value is read back correctly. This ensures synchronization from TCK to
MCLK, and from MCLK to TCK, regardless of the relative clock speeds.
Conditions for breakpoint and watchpoint generation are given in Monitor mode on
page 5-21.
B.15.2 Disabling interrupts
IRQs and FIQs are disabled under the following conditions:
• during debugging (DBGACK HIGH)
•when the INTDIS bit is HIGH.
The IFEN signal is driven as shown in Table B-8.
B.15.3 Forcing DBGRQ
Figure B-11 on page B-55 shows that the value stored in bit [1] of the debug control
register is synchronized and then ORed with the external DBGRQ before being applied
to the processor. The output of this OR gate is the signal DBGRQI which is brought out
externally from the macrocell.
The synchronization between debug control register bit [1] and DBGRQI assists in
multiprocessor environments. The synchronization latch only opens when the TAP
controller state machine is in the RUN-TEST-IDLE state. This enables an enter-debug
condition to be set up in all the processors in the system while they are still running.
When the condition is set up in all the processors, it can be applied to them
simultaneously by entering the RUN-TEST-IDLE state.
Table B-8 Interrupt signal control
DBGACK INTDIS IFEN Interrupts
0 0 1 Permitted
1 x 0 Inhibited
x 1 0 Inhibited
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