ARM ARM7TDMI - Appendix B Debug in Depth

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Appendix B

Debug in Depth

This appendix describes the debug features of the ARM7TDMI core in further detail

and includes additional information about the EmbeddedICE-RT logic. It contains the

following sections:

• Scan chains and the JTAG interface on page B-3

• Resetting the TAP controller on page B-6

• Pullup resistors on page B-7

• Instruction register on page B-8

• Public instructions on page B-9

• Test data registers on page B-14

• The ARM7TDMI core clocks on page B-22

• Determining the core and system state in debug state on page B-24

• Behavior of the program counter in debug state on page B-30

• Priorities and exceptions on page B-33

• Scan chain cell data on page B-35

• The watchpoint registers on page B-42

• Programming breakpoints on page B-47

• Programming watchpoints on page B-50

• The debug control register on page B-51

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