Instruction Cycle Timings
6-24 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Note
Coprocessor data transfer operations are not available in Thumb state.
bpc+820- 0 01 000
b+1 alu 2 1 CPdata 0 1 1 1 0 0
• alu+• 2 1 CPdata 0 1 1 1 0 0
n+b alu+• 2 1 CPdata 0 1 1 1 0 0
n+b+1 alu+• 2 1 CPdata 0 0 1 1 1 1
pc+12
Table 6-18 coprocessor data transfer instruction cycle operations (continued)
CP
register
status
Cycle Address
MA
S
[1:0]
nRW Data nMREQ SEQ nOPC nCPI CPA CPB
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