ARM ARM7TDMI - Page 132

Debug Interface
5-12 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
5.4.2 Clock switch during test
When serial test patterns are being applied to the ARM7TDMI core through the JTAG
interface, the processor must be clocked using DCLK. MCLK must be held LOW.
Entry into test is less automatic than debug and you must take care to prevent spurious
clocking on the way into test.
During test, you can use the TAP controller to serially test the processor. If scan chain
0 and INTEST are selected, DCLK is generated while the state machine is in the
RUN-TEST/IDLE state. During EXTEST, DCLK is not generated.
On exit from test, RESTART must be selected as the TAP controller instruction. When
this is done, MCLK can be resumed. After INTEST testing, you must take care to
ensure that the core is in a sensible state before reverting to normal operation. The safest
ways to do this are as follows:
• select RESTART, then cause a system reset
•insert
MOV PC, #0 into the instruction pipeline before reverting to normal
operation.