ARM ARM7TDMI - Page 130

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Debug Interface

instruction is a busy-waiting access to a coprocessor, the instruction terminates and

ARM7TDMI processor enters debug state immediately. This is similar to the action of

nIRQ and nFIQ.

5.3.2 Action of the ARM7TDMI processor in debug state

In debug state, nMREQ and SEQ indicate internal cycles. This enables the rest of the

memory system to ignore the core and function as normal. Because the rest of the

system continues to operate, the ARM7TDMI processor is forced to ignore aborts and

interrupts.

The system must not change the following signals during debug:

BIGEND If BIGEND changes during debug:

• synchronization problems are introduced

• the programmer’s view of the processor changes without the

knowledge of the debugger.

nRESET Resetting the core while debugging causes the debugger to lose

track of the core.

When the system applies reset to the ARM7TDMI processor by

driving nRESET LOW, the processor state changes with the

debugger unaware that the core has reset.

When instructions are executed in halt mode, all memory interface outputs except

nMREQ and SEQ change asynchronously to the memory system. For example, every

time a new instruction is scanned into the pipeline, the address bus changes.

The memory controller must be designed to ensure that asynchronous behavior does not

affect the rest of the system. Although the behavior of nMREQ and SEQ is

asynchronous, this does not affect the system because nMREQ and SEQ are forced to

indicate internal cycles regardless of the behavior of the rest of the core.

5.3.3 Action of the ARM7TDMI core in monitor mode

In monitor mode, the ARM7TDMI processor continues to execute instructions, and the

memory interface behaves as normal.

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