Debug in Depth
B-44 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
A register is read by shifting its address into the address field and clearing the read/write
bit.
Note
A read or write actually takes place when the TAP controller enters the UPDATE-DR
state.
The register addresses are shown in Table B-5 on page B-42.
Note
For DCC data register reads, the least significant bit of the shifted out address field is
used as a status bit, and reflects the value of bit [0] of the DCC control register. This
enables the debugger to confirm the status of the scan chain as valid read data, and the
data is read in by the debugger during a single pass of the scan chain. A separate read
of the DCC control register and the DCC data register is therefore unnecessary, and the
DCC bandwidth is increased.
B.12.2 Using the mask registers
For each value register in a register pair, there is a mask register of the same format. If
a bit is set in the mask register, the same bit in the corresponding value register is
disregarded during a comparison.
For example, when a watchpoint is required on a particular memory location, but the
data value is irrelevant, you can program the data mask register to
0xFFFFFFFF
. Setting
all bits in the data mask register causes the entire data bus field to be ignored.
Note
The mask is an XNOR mask rather than a conventional AND mask. When a bit in the
mask register is set, the comparator for that bit position always matches, irrespective of
the value register or the input value.
Clearing a bit in the mask register means that the comparator matches only if the input
value matches the value programmed into the corresponding bit of the value register.
B.12.3 The control registers
The control value and control mask registers are mapped identically in the lower eight
bits, as shown in Figure B-8 on page B-45.
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