ARM ARM7TDMI - Page 256

Debug in Depth
B-46 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
output of Watchpoint 1 is referred to the CHAIN input of
Watchpoint 0. The CHAINOUT output is derived from a register.
The address/control field comparator drives the write enable for
the register. The input to the register is the value of the data field
comparator. The CHAINOUT register is cleared when the control
value register is written, or when nTRST is LOW.
RANGE Can be referred to another watchpoint unit.
In the ARM7TDMI core EmbeddedICE-RT logic, the
RANGEOUT output of Watchpoint 1 is referred to the RANGE
input of Watchpoint 0. This enables the two watchpoints to be
coupled for detecting conditions that occur simultaneously, such
as range checking.
ENABLE When a watchpoint match occurs, the internal BREAKPT signal
is asserted only when the ENABLE bit is set. This bit exists only
in the value register. It cannot be masked.
For each of the bits [7:0] in the control value register, there is a corresponding bit in the
control mask register. These bits remove the dependency on particular signals.