Signal and Transistor Descriptions
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. A-5
BL[3:0]
Byte latch control
IC The values on the data bus are latched on the falling edge of MCLK when
these signals are HIGH. For most designs these signals must be tied HIGH.
BREAKPT
Breakpoint
IC A conditional request for the processor to enter debug state is made by
placing this signal HIGH. If the memory access at that time is an instruction
fetch, the processor enters debug state only if the instruction reaches the
execution stage of the pipeline. If the memory access is for data, the
processor enters debug state after the current instruction completes
execution. This enables extension of the internal breakpoints provided by the
EmbeddedICE-RT logic.
See Behavior of the program counter in debug state on page B-30 for details
on the use of this signal.
BUSDIS
Bus disable
O When INTEST is selected on scan chain 0, 4, or 8 this is HIGH. It can be
used to disable external logic driving onto the bidirectional data bus during
scan testing. This signal changes after the falling edge of TCK.
BUSEN
Data bus configuration
IC A static configuration signal that selects whether the bidirectional data bus
(D[31:0]) or the unidirectional data busses (DIN[31:0] and DOUT[31:0])
are used for transfer of data between the processor and memory.
When BUSEN is LOW, D[31:0] is used; DOUT[31:0] is driven to a value
of zero, and DIN[31:0] is ignored, and must be tied LOW.
When BUSEN is HIGH, DIN[31:0] and DOUT[31:0] are used; D[31:0] is
ignored and must be left unconnected.
See Chapter 3 Memory Interface for details on the use of this signal.
COMMRX
Communications channel receive
O When the communications channel receive buffer is full this is HIGH.
This signal changes after the rising edge of MCLK.
See Debug Communications Channel on page 5-17 for more information.
COMMTX
Communications channel transmit
O When the communications channel transmit buffer is empty this is HIGH.
This signal changes after the rising edge of MCLK.
See Debug Communications Channel on page 5-17 for more information.
CPA
Coprocessor absent
IC Placed LOW by the coprocessor if it is capable of performing the operation
requested by the processor.
CPB
Coprocessor busy
IC Placed LOW by the coprocessor when it is ready to start the operation
requested by the processor.
It is sampled by the processor when MCLK goes HIGH in each cycle in
which nCPI is LOW.
Table A-3 Signal descriptions (continued)
Name Type Description
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