Signal and Transistor Descriptions
A-6 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
D[31:0]
Data bus
IC
O
Used for data transfers between the processor and external memory.
During read cycles input data must be valid on the falling edge of MCLK.
During write cycles output data remains valid until after the falling edge of
MCLK.
This bus is always driven except during read cycles, irrespective of the value
of BUSEN. Consequently it must be left unconnected if using the
unidirectional data buses.
See Chapter 3 Memory Interface.
DBE
Data bus enable
IC Must be HIGH for data to appear on either the bidirectional or unidirectional
data output bus.
When LOW the bidirectional data bus is placed into a high impedance state
and data output is prevented on the unidirectional data output bus.
It can be used for test purposes or in shared bus systems.
DBGACK
Debug acknowledge
O When the processor is in a debug state this is HIGH.
DBGEN
Debug enable
IC A static configuration signal that disables the debug features of the processor
when held LOW.
This signal must be HIGH to enable the EmbeddedICE-RT logic to function.
DBGRQ
Debug request
IC This is a level-sensitive input, that when HIGH causes ARM7TDMI core to
enter debug state after executing the current instruction. This enables
external hardware to force the ARM7TDMI core into debug state, in
addition to the debugging features provided by the EmbeddedICE-RT logic.
See Appendix B Debug in Depth.
DBGRQI
Internal debug request
O This is the logical OR of DBGRQ and bit [1] of the debug control register.
DIN[31:0]
Data input bus
IC Unidirectional bus used to transfer instructions and data from the memory to
the processor.
This bus is only used when BUSEN is HIGH. If unused then it must be tied
LOW.
This bus is sampled during read cycles on the falling edge of MCLK.
Table A-3 Signal descriptions (continued)
Name Type Description
To Next Page
Loading...
