Debug Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 5-15
— debug status register
— abort status register.
• Debug Communications Channel (DCC).
The debug control register and the debug status register provide overall control of
EmbeddedICE-RT operation. The abort status register is used when monitor mode is
selected.
You can program one or both watchpoint units to halt the execution of a program by the
core. Execution halts when the values programmed into EmbeddedICE-RT match the
values currently appearing on the address bus, data bus, and various control signals.
Note
You can mask any bit so that its value does not affect the comparison.
You can configure each watchpoint unit for either a watchpoint or a breakpoint.
Watchpoints and breakpoints can be data-dependent in halt mode only.
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