ARM Cortex-M0 User Manual

Contents
vi Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
3.6 Exceptions ................................................................................................ 3-12
Chapter 4 System Control
4.1 About system control .................................................................................. 4-2
4.2 System control register summary ............................................................... 4-3
Chapter 5 Nested Vectored Interrupt Controller
5.1 About the NVIC ........................................................................................... 5-2
5.2 NVIC register summary .............................................................................. 5-3
Chapter 6 Debug
6.1 About debug ............................................................................................... 6-2
6.2 Debug register summary ............................................................................ 6-9
Appendix A Revisions
Glossary

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent