ARM Cortex-M0 User Manual

Programmers Model
3-8 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
3.3.1 Binary compatibility with other Cortex processors
The processor implements a binary compatible subset of the instruction set and features
provided by other Cortex-M profile processors. You can move software, including
system level software, from the Cortex-M0 to other Cortex-M profile processors.
To ensure a smooth transition, ARM recommends that code designed to operate on
other Cortex-M profile processor architectures obey the following rules and configure
the Configuration Control Register (CCR) appropriately:
• use word transfers only to access registers in the NVIC and System Control Space
(SCS).
• treat all unused SCS registers and register fields on the processor as
Do-Not-Modify.
• if you use an ARMv7-M processor, configure the following fields in the CCR:
— STKALIGN bit to 1
— UNALIGN_TRP bit to 1
— Leave all other bits in the CCR register as their original value.

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent