System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-64
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Figure 4-42 Slave Port Control Register bit assignments
Table 4-43 shows the Slave Port Control Register bit assignments.
To access the Slave Port Control Register, read or write CP15 with:
MRC p15, 0, <Rd>, c11, c0, 0 ; Read Slave Port Control Register
MCR p15, 0, <Rd>, c11, c0, 0 ; Write Slave Port Control Register
4.3.26 c13, FCSE PID Register
This processor does not support Fast Context Switch Extension (FCSE).
The FCSE Process IDentifier (PID) Register is accessible in Privileged mode only. This register
reads as zero and ignores writes.
4.3.27 c13, Context ID Register
The CONTEXTIDR characteristics are:
Purpose • Holds a process IDentification (ID) value for the running process.
• The Embedded Trace Macrocell (ETM) and the debug logic use this
register. The ETM can broadcast its value to indicate the process that
is running. You must program each process with a unique number.
• Enables process dependent breakpoints and instructions.
Usage constraints The CONTEXTIDR is:
• a read/write register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes The CONTEXTIDR, bits [31:0] contain the process ID number.
To use the CONTEXTIDR, read or write CP15 with:
Reserved
31 210
Privileged access
AXI slave enable
Table 4-43 Slave Port Control Register bit assignments
Bits Name Function
[31:2] - RAZ/UNP
[1] Privileged access Defines level of access for TCM accesses:
0
= Non-privileged and privileged access. This is the reset value.
1
= Privileged access only.
[0] AXI slave enable Enables or disables the AXI slave port for TCM accesses:
0
= Enables AXI slave port. This is the reset value.
1
= Disables AXI slave port.
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