System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-80
ID073015 Non-Confidential
To access the Build Options 2 Register, write CP15 with:
MRC p15, 0, <Rd>, c15, c2, 1 ; read Build Options 2 Register
[13] NO_A_TCM_INF Indicates whether the processor contains an ATCM port:
0 = processor contains ATCM port
1 = processor does not contain ATCM port.
[12] NO_B0_TCM_INF Indicates whether the processor contains a B0TCM port:
0 = processor contains B0TCM port
1 = processor does not contain B0TCM port.
[11] NO_B1_TCM_INF Indicates whether the processor contains a B1TCM port:
0 = processor contains B1TCM port
1 = processor does not contain B1TCM port.
[10] TCMBUSPARITY Indicates whether the processor contains TCM address bus parity logic:
0 = processor does not contain TCM address bus parity logic
1 = processor contains TCM address bus parity logic.
[9] NO_SLAVE Indicates whether the processor contains an AXI slave port:
0 = processor contains an AXI slave port
1 = processor does not contain an AXI slave port.
[8:7] ICACHE_ES Indicates whether an error scheme is implemented for the instruction cache:
00 = no error scheme
01 = 8-bit parity error detection
11 = 64-bit error detection and correction.
If the processor does not contain an Icache, these bits are set to 00.
[6:5] DCACHE_ES Indicates whether an error scheme is implemented for the data cache:
00 = no error scheme
01 = 8-bit parity error detection
10 = 32-bit error detection and correction.
If the processor does not contain a Dcache, these bits are set to0b00.
[4] NO_HARD_ERROR_CACHE Indicates whether the processor contains cache for corrected TCM errors:
0 = processor contains TCM error cache
1 = processor does not contain TCM error cache.
[3] AXIBUSPARITY Indicates whether the processor contains AXI bus parity logic.
0 = processor does not contain AXI bus parity logic
1 = processor contains AXI bus parity logic.
[2:0] - Undefined.
a. The value of this bit is Unpredictable in revision r1p0 of the processor.
Table 4-57 Build Options 2 Register bit assignments (continued)
Bits Name Function
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