Events and Performance Monitor
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-18
ID073015 Non-Confidential
Figure 6-10 shows the PMINTENCLR bit assignments.
Figure 6-10 PMINTENCLR Register bit assignments
Table 6-11 shows the PMINTENCLR bit assignments.
Reading this register returns the current setting, with a 1 in one of the counter bits indicating that
interrupts are enabled for that counter. Writing a 1 to a particular interrupt disable bit disables
interrupt generation on overflow of that counter. Writing a 0 has no effect. You can only enable
interrupt requests by writing to the PMINTENSET Register.
To access the PMINTENCLR Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c14, 2 ; Read PMINTENCLR Register
MCR p15, 0, <Rd>, c9, c14, 2 ; Write PMINTENCLR Register
C
31 3210
Reserved
P2
P1
P0
Performance monitor counter
overflow interrupt disables
Cycle count overflow interrupt disable
Table 6-11 PMINTENCLR Register bit assignments
Bits Name Function
[31] C PMCCNTR overflow interrupt
[30:3] - UNP on reads, SBZP on writes
[2] P2 PMC2 overflow interrupt
[1] P1 PMC1 overflow interrupt
[0] P0 PMC0 overflow interrupt
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