Level One Memory System
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-12
ID073015 Non-Confidential
When the processor is in debug halt-state, any correctable error is corrected as appropriate, but
the memory access is not repeated to fetch the correct data, therefore the instruction generating
the error does not complete successfully. Instead, the sticky synchronous abort flag in the
DBGDSCR is set. See CP14 c1, Debug Status and Control Register on page 12-14.
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