Level Two Interface
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-27
ID073015 Non-Confidential
• You must access the cache RAMs using 32-bit or 64-bit AXI transfers. Using an 8-bit or
16-bit transfer size generates a SLVERR error response.
• For reads, the starting address, ARADDRS, must be word aligned, that is,
ARADDRS[1:0] =
00
.
• For writes, you must set all write-strobes for the size of transfer, or the operation is
Unpredictable. For example, for a 32-bit transfer, WSTRBS must be either
0x0F
or
0xF0
.
• For writes, the starting address, AWADDRS, must be double-word aligned, that is,
AWADDRS[2:0] =
000
.
• For writes to either the instruction cache data RAMs or the data cache data RAMs, the
transaction must write to a multiple of 64 bits of data. Therefore for 32-bit transfers, fixed
bursts are not permitted and the number of transfers per transaction must be even, that is,
if AWSIZES=
2
, AWBURSTS must not be
0
and AWLENS must be odd.
Data RAM access
The following tables shows the data formats for cache data RAM accesses:
• Table 9-32 on page 9-28 shows the format when neither parity nor ECC is implemented
• Table 9-33 on page 9-28 shows the format when parity is implemented
• Table 9-34 on page 9-28 shows the instruction cache format when ECC is implemented
0010 Bank 1 1
0100 Bank 2 2
1000 Bank 3 3
Table 9-31 Cache data RAM bank/address decode
Inputs
RAM bank
selected
ARADDRS[18:15] ARADDRS[3]
0001 0 Bank 0
0001 1 Bank 1
0010 0 Bank 2
0010 1 Bank 3
0100 0 Bank 4
0100 1 Bank 5
1000 0 Bank 6
1000 1 Bank 7
Table 9-30 Cache tag/valid RAM bank/address decode (continued)
Inputs
RAM bank
selected
Cache
way
ARADDRS[18:15]
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