ARM Cortex-R4 - Page 251

Level Two Interface
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-28
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• Table 9-35 on page 9-29 shows the data cache format when ECC is implemented.
Table 9-32 Data format, instruction cache and data cache, no parity and no ECC
Data bit Description
[63:48] Not used, read-as-zero
[47:32] Data value, [31:16] or [63:48]
[31:16] Not used, read-as-zero
[15:0] Data value, [15:0] or [47:32]
Table 9-33 Data format, instruction cache and data cache, with parity
Data bit Description
[63:50] Not used, read-as-zero
[49] Parity bit for data value [31:24] or [63:56]
[48] Parity bit for data value [23:16] or [55:48]
[47:32] Data value, [31:16] or [63:48]
[31:18] Not used, read-as-zero
[17] Parity bit for data value [15:8] or [47:40]
[16] Parity bit for data value [7:0] or [39:32]
[15:0] Data value, [15:0] or [47:32]
Table 9-34 Data format, instruction cache, with ECC
Data bit Description
[63:52] Not used, read-as-zero
[51:48]
Upper or lower half of the ECC 64 code
a
a. If accessing bits [31:16] of the data, bits [51:48]
hold the lower half of the ECC code.
If accessing bits [63:48] of the data, bits
[51:48] hold the upper half of the ECC code.
[47:32] Data value, [31:16] or [63:48]
[31:20] Not used, read-as-zero
[19:16]
Upper or lower half of the ECC 64 code
b
b. If accessing bits [15:0] of the data, bits [19:16]
hold the lower half of the ECC code.
If accessing bits [47:32] of the data, bits
[19:16] hold the upper half of the ECC code.
[15:0] Data value, [15:0] or [47:32]