Level Two Interface
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-29
ID073015 Non-Confidential
Tag RAM access
The following tables show the data formats for tag RAM accesses:
• Table 9-36 shows the format for read accesses when neither parity nor ECC is
implemented
• Table 9-37 on page 9-30 shows the format for read accesses when parity is implemented
• Table 9-38 on page 9-30 shows the format for read accesses when ECC is implemented
• Table 9-39 on page 9-30 shows the format for write accesses when neither parity nor ECC
is implemented
• Table 9-40 on page 9-30 shows the format for write accesses when parity is implemented
• Table 9-41 on page 9-31 shows the format for write accesses when ECC is implemented.
Table 9-35 Data format, data cache, with ECC
Data bit Description
[63:55] Not used, read-as-zero
[54:48]
ECC 32 code
a
[47:32] Data value, [31:16] or [63:48]
[31:23] Not used, read-as-zero
[22:16] ECC 32 code
[15:0] Data value [15:0] or [47:32]
a. For a 64 bit access, the ECC bits are
duplicated in bits [22:16] and bits
[54:48], and the two copies are
identical. For a 32 bit access, the ECC
bits refer to the whole 32 bit data
value, even though only 16 bits of
data are accessed.
Table 9-36 Tag register format for reads, no parity or ECC
Data bit Description
[63:55] Not used, read-as-zero
[54] Valid, way 2/3
[53:32] Tag value, way 2/3
[31:23] Not used, read-as-zero
[22] Valid, way 0/1
[21:0] Tag value, way 0/1
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