ARM Cortex-R4 - Page 253

Level Two Interface
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 9-30
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Table 9-37 Tag register format for reads, with parity
Data bit Description
[63:56] Not used, read-as-zero
[55] Parity, way 2/3
[54] Valid, way 2/3
[53:32] Tag value, way 2/3
[31:24] Not used, read-as-zero
[23] Parity, way 0/1
[22] Valid, way 0/1
[21:0] Tag value, way 0/1
Table 9-38 Tag register format for reads, with ECC
Data bit Description
[63:62] Not used, read-as-zero
[61:55] ECC, way 2/3
[54] Valid, way 2/3
[53:32] Tag value, way 2/3
[31:30] Not used, read-as-zero
[29:23] ECC, way 0/1
[22] Valid, way 0/1
[21:0] Tag value, way 0/1
Table 9-39 Tag register format for writes, no parity or ECC
Data bit Description
[63:23] Not used, read-as-zero
[22] Valid, all ways
[21:0] Tag value, all ways
Table 9-40 Tag register format for writes, with parity
Data bit Description
[63:24] Not used, read-as-zero
[23] Parity. all ways
[22] Valid, all ways
[21:0] Tag value, all ways