Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-16
ID073015 Non-Confidential
[19] Discard
asynchronous
abort
This bit controls how the processor handles asynchronous data aborts when in halting
debug mode:
0 = aborts are handled as normal
1 = the sticky asynchronous abort bit is set on an asynchronous abort but no other action
is taken.
The processor automatically sets this bit on entry into halting debug state and clears it on
exit from halting debug state.
[18-16] - RAZ on reads, SBZP on writes.
[15] Monitor mode The Monitor debug-mode enable bit:
0 = Monitor debug-mode disabled, this is the reset value
1 = Monitor debug-mode enabled.
If Halting debug-mode is enabled through bit [14], then the processor is in Halting
debug-mode regardless of the value of bit [15]. If the external interface input DBGEN is
LOW, this bit reads as 0. The programmed value is masked until DBGEN is HIGH, and
at that time the read value reverts to the programmed value.
[14] Halting mode The Halting debug-mode enable bit:
0 = Halting debug-mode disabled, this is the reset value
1 = Halting debug-mode enabled.
If the external interface input DBGEN is LOW, this bit reads as 0. The programmed value
is masked until DBGEN is HIGH, and at that time the read value reverts to the
programmed value.
[13] ARM Execute ARM instruction enable bit:
0 = disabled, this is the reset value
1 = enabled.
If this bit is set and an DBGITR write succeeds, the processor fetches an instruction from
the DBGITR for execution. If this bit is set to 1 when the processor is not in debug state,
the behavior of the processor is Unpredictable.
[12] Comms CP14 debug user access disable control bit:
0 = CP14 debug user access enable, this is the reset value
1 = CP14 debug user access disable.
If this bit is set and a User mode process attempts to access any CP14 debug registers, an
Undefined Instruction exception is taken.
[11] IntDis Interrupts disable bit:
0 = interrupts enabled, this is the reset value
1 = interrupts disabled.
If this bit is set, the IRQ and FIQ input signals are inhibited. The external debugger can
optionally use this bit to execute pieces of code in normal state as part of the debugging
process to avoid having an interrupt taking control of the program flow. For example, the
debugger might use this bit to execute an OS service routine to bring a page from disk into
memory. It might be undesirable to service any interrupt during the routine execution.
[10] DbgAck DbgAck bit. If this bit is set to 1, the DBGACK output signal is forced HIGH, regardless
of the processor state. The external debugger can optionally use this bit to execute pieces
of code in normal state as part of the debugging process for the system to behave as if the
processor is in debug state. Some systems rely on DBGACK to determine whether data
accesses are application or debugger generated. This bit is 0 on reset.
[9] - RAZ on reads, SBZP on writes.
Table 12-10 DBGDSCR Register bit assignments (continued)
Bits Name Function
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