Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-15
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[28] - RAZ on reads, SBZP on writes.
[27] DTRRXfull_l The latched DTRRXfull flag. This is the last value of DTRRXfull that the debugger read.
It is set to the value of DTRRXfull on a debugger read of the DBGDSCR.
This flag controls how the DBGDTRRX is written by a debugger. See DTR access mode
on page 12-18 for more information.
The value read for this bit depends on the state of the locked bit in the DBGLSR and the
PADDRDBG31 value used for the read. If the locked bit is set, and PADDRDBG31 is 0,
then this bit reads as the DTRRXfull_l value. Otherwise it reads as the DTRRXfull value.
[26] DTRTXfull_l The latched DTRTXfull flag. This is the last value of DTRTXfull that the debugger read.
It is set to the value of DTRTXfull on a debugger read of the DBGDSCR.
This flag controls how the DBGDTRTX is read by the debugger. See DTR access mode
on page 12-18 for more information.
The value read for this bit depends on the state of the locked bit in the DBGLSR and the
PADDRDBG31 value used for the read. If the locked bit is set and PADDRDBG31 is 0,
then this bit reads as the DTRTXfull_l value. Otherwise it reads as the DTRTXfull value.
[25] PipeAdv Sticky pipeline advance read-only bit. This bit enables the debugger to detect whether the
processor is idle. In some situations, this might mean that the system bus port is
deadlocked. This bit is set to 1 when the processor pipeline retires one instruction. It is
cleared by a write to DBGDRCR[3].
0 = no instruction has completed execution since the last time this bit was cleared
1 = an instruction has completed execution since the last time this bit was cleared.
[24] InstrCompl_l The latched instruction complete read-only bit. This flag determines whether the processor
has completed execution of an instruction issued by the debugger, through the DBGITR.
0 = processor is executing an instruction fetched from the DBGITR Register
1 = processor is not executing an instruction fetched from the DBGITR Register.
Entry into halting debug state sets this flag to 1. When the processor is not in halting debug
state, the value of this flag is Unpredictable.
This flag controls debugger writes to the DBGITR:
• If DBGDSCR[21:20] is equal to 0, then writes to the DBGITR are ignored when
InstrCompl_l is 0.
• If DBGDSCR[21:20] is not equal to 0 then debugger writes to the DBGITR are
stalled until InstrCompl_l is 1.
[23:22] - RAZ on reads, SBZP on writes.
[21:20] DTR access DTR access mode. You can use this field to optimize DTR traffic between a debugger and
the processor.
b00 = Non-blocking mode. This is the default.
b01 = Stall mode
b10 = Fast mode
b11 = Reserved.
• This field only affects the behavior of DBGDSCR, DTR, and DBGITR accesses
through the APB port, and not through CP14 debug instructions.
• Non-blocking mode is the default setting. Improper use of the other modes might
result in the debug access bus becoming deadlocked.
See DTR access mode on page 12-18 for more information.
Table 12-10 DBGDSCR Register bit assignments (continued)
Bits Name Function
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