Signal Descriptions
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. A-15
ID073015 Non-Confidential
B1TCADDR [22:3] Output CLKIN Address for B1TCM data RAM
B1TCBYTEWR [7:0] Output CLKIN Byte strobes for direct write
B1TCSEQ Output CLKIN B1TCM RAM access is sequential
B1TCDATAOUT [63:0] Output CLKIN Write data for B1TCM data RAM
B1TCPARITYOUT [13:0] Output CLKIN Write parity or ECC code for B1TCM
B1TCACCTYPE[2:0] Output CLKIN Determines access type:
b001 = Load/Store
b010 = Fetch
b100 = DMA
b100 = MBIST
c
.
a. This signal is ignored when bit [2] of the Auxiliary Control Register is set to 0, see c1, Auxiliary Control Register
on page 4-40.
b. Only generated if the processor is configured to include TCM address bus parity.
c. The MBIST interface has no way of signaling a wait. If it is accessing the TCM, and the TCM signals a wait, the
AXI slave pipeline stalls and the data arrives later. However, no signal is sent to the MBIST controller to indicate
this.
Table A-10 B1TCM port signals (continued)
Name Direction Clocking Description
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