Functional Description
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 2-18
ID073015 Non-Confidential
You can enable error checking and 64-bit store behavior on a per-TCM interface basis.
References to these controls relate to whichever TCM is being initialized.
Using TCMs from reset
The processor can be pin-configured to enable the TCM interfaces from reset, and to select the
address at which each TCM appears from reset. See TCM initialization on page 8-16 for more
information. This enables you to configure the processor to boot from TCM but, to do this, the
TCM must first be preloaded with the boot code. The nCPUHALT pin can be asserted while
the processor is in reset to stop the processor from fetching and executing instructions after
coming out of reset. While the processor is halted in this way, the TCMs can be preloaded with
the appropriate data. When the nCPUHALT pin is deasserted, the processor starts fetching
instructions from the reset vector address in the normal way.
When it is deasserted to start the processor fetching, nCPUHALT must not be asserted again
except when the processor is under processor or power-on reset, that is, nRESET asserted. The
processor does not halt if the nCPUHALT pin is asserted while the processor is running.
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