Functional Description
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 2-17
ID073015 Non-Confidential
Write to TCM directly from debugger
A Debug Access Port (DAP) in the system is used to generate AMBA
transactions to write data into the TCMs through the AXI slave interface. This
DAP is controlled from the debug host through a JTAG chain.
Preloading TCMs with parity or ECC
The error codes or parity bits in the TCM RAM, if configured with an error scheme, are not
initialized by the processor. Before a RAM location is read with ECC or parity checking
enabled, the error codes or parity bits must be initialized. To calculate the error code or parity
bits correctly, the logic must have all the data in the data chunk that those bits protect. Therefore,
when the TCM is being initialized, the writes must be of the same width and aligned to the data
chunk that the error scheme protects.
You can initialize the TCM RAM with error checking turned on or off, according to the
following rules. See c1, Auxiliary Control Register on page 4-40. The error code or parity bits
written to the TCM are valid for the data provided, even if the error checking is turned off.
If you initialize the TCM using the slave port, you must use write transactions to write to the
TCM memory as follows:
• If the error scheme is parity, any write transaction can be used.
• If the error scheme is 32-bit ECC, the write transaction must start at a 32-bit aligned
addresses and write a continuous block of memory, containing a multiple of 4 bytes. All
bytes in the block must be written, that is, have their byte lane strobe asserted.
• If the error scheme is 64-bit ECC, the write transaction must start at a 64-bit aligned
addresses and write a continuous block of memory, containing a multiple of 8 bytes. All
bytes in the block must be written, that is, have their byte lane strobe asserted.
If initialization is done by running code on the processor, this is best done by a loop of stores
that write to the whole of the TCM memory as follows:
• If the error scheme is parity, or no error scheme, any store instruction can be used.
• If the scheme is 32-bit ECC, use Store Word (STR), Store Two Words (STRD), or Store
Multiple Words (STM) instructions to 32-bit aligned addresses.
• If the scheme is 64-bit ECC, use
STRD
or
STM
that has an even number of registers in the
register list, with a 64-bit aligned starting address.
You can use the alignment-checking features of the processor to help you ensure that memory
accesses are 32-bit aligned, but there is no checking for 64-bit alignment. If you are using
STRD
or
STM
, an alignment fault is generated if the address is not 32-bit aligned. For the same behavior
with
STR
instructions, enable strict-alignment-checking by setting the A-bit in the SCTLR. See
c1, System Control Register on page 4-37.
If the error scheme is 64-bit ECC, a simpler way to initialize the TCM is:
• Ensure error checking is off.
• Turn on 64-bit store behavior using CP15. See c15, Secondary Auxiliary Control Register
on page 4-43.
• Write to the TCM using any store instructions, or any AXI write transactions. The
processor performs read-modify-write accesses to ensure that all writes are to 64-bit
aligned quantities, even though error checking is turned off.
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