System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-43
ID073015 Non-Confidential
To access the ACTLR, read or write CP15 with:
MRC p15, 0, <Rd>, c1, c0, 1 ; Read ACTLR
MCR p15, 0, <Rd>, c1, c0, 1 ; Write ACTLR
4.3.17 c15, Secondary Auxiliary Control Register
The Secondary Auxiliary Control Register characteristics are:
Purpose Controls:
• branch prediction
• performance features
• error and parity logic.
Usage constraints The Secondary Auxiliary Control Register is:
• a read/write register
• accessible in Privileged mode only.
[8] FDSnS Force data side to not-shared when MPU is off:
0 = Normal operation. This is the reset value.
1 = Data side normal Non-cacheable forced to Non-shared when MPU is off.
[7] sMOV sMOV of a divide does not complete out of order. No other instruction is issued until the
divide is finished.
0 = Normal operation. This is the reset value.
1 = sMOV out of order disabled.
[6] DILS Disable low interrupt latency on all load/store instructions.
0 = Enable LIL on all load/store instructions. This is the reset value.
1 = Disable LIL on all load/store instructions.
[5:3] CEC Cache error control for cache parity and ECC errors.
See Table 8-2 on page 8-21 and Table 8-3 on page 8-22 for information about how these bits
are used. The reset value is b100.
[2] B1TCMECEN B1TCM external error enable:
0 = Disabled
1 = Enabled.
The primary input ERRENRAM[2] defines the reset value.
[1] B0TCMECEN B0TCM external error enable:
0 = Disabled
1 = Enabled.
The primary input ERRENRAM[1] defines the reset value.
[0] ATCMECEN ATCM external error enable:
0 = Disabled
1 = Enabled.
The primary input ERRENRAM[0] defines the reset value.
a. See Dual issue on page C-34
b. See Configuration signals on page A-4.
c. This bit is only supported if parity error generation is implemented in your design.
Table 4-24 ACTLR Register bit assignments (continued)
Bits Name Function
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