9-12 Series 90-30 PLC Installation and Hardware Manual
–
August 2002 GFK-0356Q
9
module configuration at power-up and periodically throughout the operation. The actual
configuration must match the programmed configuration. Any detected deviations are reported to
the CPU alarm processor function for the configured fault response. Refer to GFK-056, the
Series
90-30 State Logic CPU User’s Manual
for more information.
Table 9-1. System Specifications for Series 90-30 State Logic CPUs
State Logic CPU Model
CSE 340 CSE 331 CSE 313/323 CSE 311
Digital Inputs, %I
024 024 5252
Digital Outputs, %Q
024 024 5252
Global I/O, %G
280 280 280 280
Internal Flags
000 000 500 500
Analog Inputs, %AI
256 256 28 28
Analog Outputs, %AQ
28 28 64 64
PID Loops
20 20 20 20
Integer Variables
000 000 250 250
Floating Point Variables
250 250 6 6
String Variables
20 20 8 8
Character Variables
64 64 64 64
Tables
20 20 0 0
Program Memory
98K Bytes 48K Bytes 20K Bytes 0K Bytes
Processor Speed
20 MHz 0 MHz 0 MHz 0 MHz
Number of Baseplates
55
Baseplate Size
5 or 0 slots 5 or 0 slots 5 slots (CSE33)
0 slots (CSE323)
5 slots
Supports SCM
Yes Yes No No
Serial Ports
Clock/Calendar
Hardware Hardware Software Software
Table Memory Space
4K Bytes 4K Bytes K Bytes K Bytes
For more detailed information on State Logic CPU specifications, see GFK-056, the
Series 90-30
State Logic Control System User’s Manual
.