3.7.3
Command Timing and Completion
This section describes, for each devicedependent command, whether that command
is
performed
in
an
overlapped
or sequentral manner.
In
other words, it states whether the next
command
may
begin
while this
cod
is
being
executed, or
if
the next command must wait
until
this
command
is completed before its execution
begins.
The
conditions for setting the operation complete flag
are
given
in
Section
3.7.2.
All
LDC-3700
Series Laser Diode Controller devicedependent commands
are
executed in an overlapped manner,
and the operation complete flag is set after the conditions outlined
in
Section
3.7.2
have been satisfied.
The
*WAI
(common command) is
an
example of a sequential
command
which forces the next command to wait
until the no-operation-pending flag is true. This is essentially the same
as
waiting for the
OPC
flag to become true,
because
the noperations-pending flag is
used
to set the
OPC
flag (bit
0
of the
Standard
Event
Status
Register).
In normal operation, the overlapped commands execute faster
than
would
appear
by
querying the
OPC
flag. This is
due to the
nature
of the non-volatile memory storage process.
Commands
which
change the
status
of the
instrument limits, or change its mode or current range, step value, or
status
enable registers,
will
not have their
OPC
flag set until all current writing to non-volatile memory has
been
completed. This is done to ensure that the
OPC
flag is never set prematurely. However,
in
most
cases, the
individual
operation
will
be
completed
immdately.
The
speed
of writing to non-volatile memory
(EEPROM)
is slow compared to processor
speed,
and the new
information (to
be
written) is placed on a queue
to
reduce the processor overhead for non-volatile storage
operations. However, the new information (eg new parameter value) is buffered
and
is essentially stored
as
soon
as
the command which created it is
parsed.
Therefore, even though the
OPC
flag
may
not
be
set
immediately
after
a new parameter value is created, the new value is stored for
all
intents and
purposes,
and command throughput is
not directly related to the
OPC
rate.
Whenever there is
any
output (response)
data
in the Output Queue, bit
4
is set in the Status Byte Register.
Whenever there is any error message
in
the Error Queue, bit
7
is set
in
the
Status
Byte
Register.
3.8
Output
Off
Registers
The Output
Off
Enable Registers allow the user to determine which conditions and events in the
TEC
and LASER
controllers will
cause
their outputs to be
turned
off. These registers are configured
in
a manner which is similar to
the
status
reporting registers. However, their outputs are not reported in the Status Byte Register. Rather,
they
go to
the hardware which controls the output switching. The events and conditions which may
be
set
to
cause
the
TEC
and
LASER outputs to
be
turned
off are shown in
Figures
3.12
and
3.13.
The default (factory) settings for these regwters are shown
in
Table
3.2.
These
settings
are not
effected
by
the *PSC
Power-On Status
Clear)
command.
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