Intel 6 SERIES

Development Kit Features
2
nd
Generation Intel
®
Core™ Processor with Intel
®
6 Series Chipset Development Kit
User Guide March 2011
28 Document Number: 325208-001
Strap 0 1
CFG4
An eDP panel device is
connected to eDP port (Short
J1E1 – (1-2))
No Display Port connected to eDP
(default—J1E1- (1-X))
3.1.5.2 External Graphics Support
The development board supports external graphics through an on-board PCIe graphics
x16 slot. This interface is fully compliant to the PCIe Base Specification Revision 2.0.
The board supports Gen 2 (5.0 GT/s) PCIe frequencies.
Switchable Graphics is also supported on the board. It can be validated using the Elk
Creek add-in card.
Table 6. CFG[6] and [5] Straps Combined and Used for PEG Interface Configuration
Strap 11 10
CFG[6:5]
X16 PEG interface (Default-
UNSTUFF R2R31, R2R25)
PEG 2x8 bifurcation enabled
(STUFF R2R31)
Table 7. Other PEG Interface Straps
Strap 0 1
CFG2 Lane-reversed (STUFF R2R47) Not lane-reversed. (Default)
CFG7
PEG wait for BIOS for training
(STUFF R2R20)
PEG training followed by RST#
deassertion (Default -
UNSTUFF R2R0)
NOTE: The processor supports lane-reversal of the PEG lanes, but the development board uses
non-lane-reversed routing.
3.1.5.3 Direct Media Interface (DMI)-2 Interface
The development board supports x4 DMI-2 bidirectional lanes (four lanes in each
direction) between the processor and PCH. DMI is the key interface between the
processor and the Intel
®
6 Series Chipset. Apart from this, it is also used to transfer
information such as ME data, and power-management signals such as SLP#,
DPRSLP#, DPRSLPVR#, STP_CLK#. All the power-management handshakes happen
across this interface. The board supports a maximum speed of 5 GT/s (Gen 2 speed).
The series resistors in the path of FDI/DMI lanes for earlier platforms are removed in
the development board.
3.1.6 Intel
®
Flexible Display Interface (Intel
®
FDI)
Intel FDI is a dedicated link to transmit the display-related pixel information over
unidirectional 2x4 lanes from processor to PCH. The maximum supported speed for