Intel 6 SERIES

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Development Kit Features

Generation Intel

Core™ Processor with Intel

6 Series Chipset Development Kit

March 2011 User Guide

Document Number: 325208-001 31

Figure 3. PCIe* Port Mapping – Schematic Snapshot

Main Page

Table of Contents3
About this Document7
Content Overview7
Text Conventions7
Table 1. Text Conventions7
Glossary of Terms and Acronyms9
Table 2. Terms9
Table 3. Acronyms11
Related Documents and Information14
Development Kit Technical Support15
Online Support15
Additional Technical Support15
Table 4. Related Documents and Information15
Getting Started16
Development Kit Contents16
Additional Required Hardware Not Included in this Kit16
Additional Required Software Not Included in this Kit17
Workspace Preparation18
System Setup18
System Power-Up19
System Power-Down19
System BIOS19
Configuring the BIOS20
Programming BIOS Using a Bootable USB Device20
Development Kit Features22
Figure 1. Development Board Block Diagram22
Table 5. Development Board Feature Description22
Processor Support24
Clock Requirements25
Processor Voltage Regulator25
SVID Supported in Intel ® MVP-7 Voltage Regulator25
Power Management and Key Signals25
Memory Support26
Graphics Support27
Internal Graphics Support27
Figure 2. Side View of Stacked SODIMM Slots27
External Graphics Support28
Direct Media Interface (DMI)-2 Interface28
Fdi)28
Table 6. CFG[6] and [5] Straps Combined and Used for PEG Interface Configuration28
Table 7. Other PEG Interface Straps28
Processor Thermals29
Processor Active Cooling29
PCH Support29
Introduction to the Intel ® 6 Series Chipset29
Key Power Management Signals29
Pcie* Support30
Table 8. Pcie* Ports30
Figure 3. Pcie* Port Mapping - Schematic Snapshot31
On-Board LAN32
Table 9. Reworks for Different Port Mappings32
Soft Audio and Modem33
Realtek* Audio Card Support33
Figure 4. On-Board LAN Block Diagram33
Table 10. Selection of I/O Voltage for the Intel33
SATA Storage34
Displays34
Table 11. SATA Ports34
Figure 5. Back Panel Connectors35
DP/HDMI Support36
Figure 6. Display Ports On-Board36
DMC Support37
Switchable Graphics37
Figure 7 Mini Pcie Connector Soldered in Place of DMC37
USB Connectors38
Usb2.038
Figure 8. Switchable Graphics with Edp from PCH38
Table 12. USB Port Mapping39
LPC Super I/O (SIO)/LPC Slot40
Serial Port, Irda40
System Management Controller (Smc)/Keyboard Controller (KBC)40
Table 13. USB2.0 Ports40
Spi41
Multi-BIOS Support41
Table 14. Jumper Settings for SPI Programming41
Clocks42
Table 15. Multi-BIOS Implementation42
CPU_ITP Clock and XDP Clock43
Figure 9. Clock (Integrated Mode) Block Diagram43
Figure 10. Block Diagram of GDXC and XDP Clock on the Development Board43
Real Time Clock44
Figure 11. Layout Snapshot for Reworks for GDXC and XDP Clock Options On-Board44
Debug Interfaces45
Processor and PCH Debug45
Chassis45
Power Supply Solutions, Usage, and Recommendations45
Power Supply Solutions45
Power Supply Usage and Recommendation46
Power Management47
Power Management States47
Table 16. Development Board Power Management States47
Development Board Summary48
Features48
Figure 12. Development Board Components - Top View48
Table 17. Development Board Components List - Top View49
Figure 13. Development Board Components - Bottom View50
Table 18. Development Board Components List - Bottom View50
Connectors51
Back Panel Connectors51
Figure 14. Back Panel Connectors51
Table 19. Back Panel Connectors51
Configuration Settings52
Configuration Jumpers/Switches52
Table 20. Configuration Jumper/Switches52
Power on and Reset Button53
Leds54
Table 21. Power on and Reset Button54
Table 22. Other Development Board Switches54
Table 23. Development Board Leds54
Quick Start56
Required Peripherals56
Instructions to Flash BIOS to SPI56
H8 Programming56
Key Jumpers57
Table 24. H8 Programming Jumpers57
Figure 15. Jumpers for Programming SPI and H858
Table 25. Key Jumpers58

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