Intel 6 SERIES

Development Kit Features
2
nd
Generation Intel
®
Core™ Processor with Intel
®
6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 43
Figure 9. Clock (Integrated Mode) Block Diagram
NOTE: Buffered-through mode, in which CK505 sources all platform clocks, is not supported in
the 2nd Generation Intel
®
Core™ processor family and Intel
®
6 Series Chipset platform.
3.2.12.3 CPU_ITP Clock and XDP Clock
The clock configuration for the clock to XDP and the clock for top-side probing
(GDXC connected to CPU_ITP pins of the processor) is SRC8 from CPT with FCIM
(Fully Integrated Clocking Mode).
The development board has certain back-up stuffing options for Buffered-through
mode. The following figures and tables present the various options.
Figure 10. Block Diagram of GDXC and XDP Clock on the Development Board