Intel 6 SERIES

Development Kit Features
2
nd
Generation Intel
®
Core™ Processor with Intel
®
6 Series Chipset Development Kit
User Guide March 2011
30 Document Number: 325208-001
• DRAMPWROK: Power good signal for DDR.
• APWROK: Indicates that the ME rails to PCH are stable.
• SYS_PWROK: Signal indicates that all platform Power Rails to PCH are stable.
• PLT_RST#: Platform Reset Signal indicated by CR5H1.
3.2.3 PCIe* Support
The development board supports six on-board PCIe (5x1 and 1x4) slots. The Intel 6
Series chipset has a total of eight Gen 2 PCIe ports. By default, four of those IO ports
have been routed to x1 connectors, one to a x4 connector, one to LAN, one to Display
Mini PCIe connector, and one to docking.
Slot 1 and 2 are in-line and close to the PCH. Slots 3 and 4 are in line and close to the
processor. Slot 5 is a x4 slot.
Table 8. PCIe* Ports
PCIe Port Default Destination
Non-Default
Destination
1 PCIe Slot 1 (J6C2) -
2
PCIe Slot 2 (J6D2) (in-line
with Slot 1)
-
3 PCIe Slot 3 (J7C1) -
4 PCIe Slot 4 (J7D2) -
5 PCIe Slot 5 (J6C1) -
6 LAN (EU7M1) PCIe Slot 5 (J6C1)
7 DOCKING (J9C1)
PCIe Slot 5 (J6C1)
PCIe Slot 6 (J8C1)
8
DISPLAY MINI PCIe
Connector(J7M1)
PCIe Slot 5 (J6C1)
DOCKING (J9C1)
More details on the reworks to be done for different destinations of the PCIe ports are
given below.