About This Document
2
nd
Generation Intel
®
Core™ Processor with Intel
®
6 Series Chipset Development Kit
User Guide March 2011
14 Document Number: 325208-001
Acronym Definition
PWM Pulse width modulation
RAID Redundant Array of Inexpensive Disks
rPGA Reduced pitch Pin Grid Array
RTC Real Time Clock
SATA Serial ATA
SIO Super Input/Output
SKU Stock Keeping Unit
SMC System Management Controller
SMBus System Management Bus
SO-DIMM Small Outline Dual In-line Memory Module
SOIC Small-Outline Integrated Circuit
SPD Serial Presence Detect
SPI Serial Peripheral Interface
SPWG Standard Panels Working Group - http://www.spwg.org/
SSO Simultaneous Switching Output
SUT System Under Test
STR Suspend To RAM
TCO Total Cost of Ownership
TCP Transmission Control Protocol
TPM Trusted Platform Module
TDM Time Division Multiplexed
TDR Time Domain Reflectometry
UDP User Datagram Protocol
UHCI Universal Host Controller Interface
USB Universal Serial Bus
VGA Video Graphics Adapter
VID Voltage Identification
VREG or VR Voltage Regulator
XDP eXtended Debug Port
1.4 Related Documents and Information
Table 4 provides a summary of available Intel classified documents and information
related to this development kit. To obtain, please contact your Intel representative.