3. Development Kit Setup
The instructions in this chapter explain how to setup the Agilex 7 FPGA I-Series
Transceiver Development Kit for specific use cases.
3.1. Default Settings
The Agilex 7 FPGA I-Series Transceiver Development Kit ships with its board switches
preconfigured to support the design examples in the kit. If you suspect that your
board might not be correctly configured with the default settings, follow the
instructions in the Factory Default Switch Settings table to return to its factory
settings before proceeding ahead.
Note: "X" refers to Don't Care in the table below.
Table 4. Factory Default Switch Settings
Switch Default Position Default Function
S19[1:4] OFF/OFF/ON/ON FPGA and system MAX 10 selected in the JTAG chain.
S20[1:4] ON/ON/ON/ON Mode 1: On-board Intel download circuit act as the only JTAG
Master.
S9[1:4] ON/OFF/OFF/X AS mode (default
setting)
OFF/ON/ON/X Avalon
®
streaming
interface x8 mode
Agilex FPGA Mode Select pins.
Default—JTAG
S10[1:4] ON/ON/ON/ON SYS_SW[0:3]
SYS_SW[0]—Factory Load
• ‘0’: Load image from Page 0 of the QSPI.
S15[1:4] ON/ON/ON/OFF SYS_SW[4:7]
• SYS_SW[4]—X
• SYS_SW[5]—FMC-A PCIe RP/EP Select.
— “0”: RP (Default)
— “1”: EP
• SYS_SW[6]—FMC-B PCIex RP/EP Select
— “0”: RP (Default)
— “1”: EP
• SYS_SW[7]—Not used
— “0”: RP
— “1”: EP (Default)
S1[1:4]
S6[1:4]
OFF/OFF/OFF/OFF
OFF/OFF/OFF/OFF
User Switch [0:3]
User Switch [4:7]
S22[1:4] ON/ON/ON/ON MUX_DIP_SW[0:3]
continued...
776646 | 2024.11.21
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