Intel Altera Agilex 7 - Block Diagram; Feature Summary

1.1. Block Diagram
Figure 2. Agilex 7 FPGA I-Series Transceiver Development Kit Block Diagram
USB
Type-B
UBII/PWR
MAX® 10
FPGA
SDM DC
DDR4 x5
(MT40A2G16SKL)
Avalon Streaming x16
GPIOs
JTAG
JTAG
EN
PG
PWR_MAX10_I2C
DIFF (x34)
FMC+_A
QSFP-DD0
QSFP-DD800
QSFP0
QSFP-DD1
SFP
QSFP1
FGTQ[3:0](x16)
FGTQ[3:2](x8)
FGTQ[0](x4)
FHT(x4)
FGTQ[3:2](x8)
FGTQ[1](x4)
FHT(x4)
FGTQ[0](x4)
FGT
12A
FGT
12B
FGT
12C
FHT
FHT
FHT
FGT
13A
FGT
13B
FGT
13C
FHT
FHT
FHT
System
MAX 10
FPGA
SYS_MAX_I2C
JTAG
Hyper RAM
Flash 2GB x2
QSFP2
MCIO
QSFP-DD2
QSFP-DD3
OSFP
FMC+
FHT(x4)
FGTQ[3:2](x8)
FGTQ[0](x4)
FGTQ[3:2](x8)
FGTQ[0](x4)
FGTQ[0:3](x16)
FHT(x4)
DIFF (x34)
I2C
CLK
PLL/
Clock
1DPC DIMM
Temp
Sensor
Voltage/
Current
Sensor
Power
Delivery
Network
EN
PG
V
IN
V
OUT
PWR_MAX10_I2C
SYS_MAX_I2C
12A
12B
12C
13A
13B
13C
EMIB EMIB EMIB
EMIBEMIBEMIB
Agilex™ 7 FPGA
I-Series
(6x F-Tile)
ESRAM
Crypto
2C
2B
2A
Crypto
SDM
ESRAM
Crypto
3C
3B
3A
Crypto
ESRAM
x72
16GB
1.2. Feature Summary
• Agilex 7 I-Series FPGA, 4047 KLE, 3948A package
• F-Tile 1 (12A):
— 16 FGT transceiver channels fan out to FPGA Mezzanine Card Plus (FMC+)
connector
• F-Tile 2 (12B):
— 4 FHT transceiver channels fan out to Quad Small Form Factor Pluggable
Double Density 800 (QSFP-DD800) connector
— 8 FGT transceiver channels to Quad Small Form Factor Pluggable Double
Density (QSFP-DD) connector
— 4 FGT Transceiver channels to Quad Small Form Factor Pluggable (QSFP)
connector
• F-Tile 3 (12C):
— 4 FHT transceiver channels fan out to QSFP-DD800 connector
— 8 FGT transceiver channels to QSFP-DD connector
— 4 FGT Transceiver channel to Small Form Factor (SFF) connector
— 4 FGT transceiver to channels to QSFP connector
• F-Tile 4 (13A):
— 4 FGT Transceiver to channels to QSFP connector
— 8 FGT transceiver channels to QSFP-DD connector
1. Overview
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Agilex
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7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
5