Connector/Switch Description
J16 1PPS IN connector
J14 1PPS OUT connector
J56 CY7C68013A I
2
C connector
J11 JTAG connector
J10 USB2.0 connector
J154 12 V hotswap I
2
C connector
S19 JTAG selection switch
S20 MSTR switch
S21 PMBUS I
2
C switch
S9 Mode selection switch
S22 MUX_DIP_SW
S10, S15 System switch
S6, S1 User switch
S7 Board power on/off switch
A.2. System Management
Two MAX 10 FPGAs (10M16SCU324C8G) are used for system management. System
MAX 10 acts as system controller. It handles FPGA AvST configuration, I2C bus access,
fan speed control and system reset functions. The UB2/PWR MAX 10 acts as Power
manager and on-board JTAG controller. Refer to below description for each function:
• Power management: Control systems and FPGA power up and optional down
sequence, supervise power regulators/switches status and manage power faults,
supervise temperature sensor interrupt signals and manage temperature faults.
• JTAG controller: Manage JTAG chain topology, JTAG master source and JTAG
slaves by S19.
Table 7. JTAG Master Sources
Schematic Signal Name Description
EXT_JTAG_TCK/TDO/TMS/TDI
JTAG header J11 for Intel FPGA Download Cable
FX2_Dp/n
Input port J10 for on-board Intel download circuit
Mode S20[4:1] S19 [4][3] [2] [1]
On: bypass from chain
Off: enable in chain
Function
000 ON/ON/ON
(Default)
S19.1 (SDM+HPS)
S19.2 (SysMax)
S19.3(FMC_B)
S19.4 (FMC_A)
Mode 1: On-board Intel download circuit
act as the only JTAG Master.
Chained HPS with SDM nodes internally.
Mode 3: External Intel FPGA Download
Cable act as the only JTAG Master.
Chained HPS with SDM nodes internally.
001 ON/ON/OFF SDM is always enabled in the
JTAG chain
Mode 2: On-board Intel download circuit
act as the only JTAG Master.
continued...
A. Development Kit Components
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