EasyManua.ls Logo

Intel Altera Agilex 7 - Custom Projects for the Development Kit; Add Smartvid Settings in the Quartus Prime QSF File; Golden Top

Intel Altera Agilex 7
69 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
6. Custom Projects for the Development Kit
6.1. Add SmartVID Settings in the Quartus Prime QSF File
The Agilex 7 silicon that is assembled on this development kit enables the SmartVID
feature by default. To avoid the Quartus Prime software from generating an error due
to incomplete SmartVID settings, you must put constraints outlined below into the
Quartus Prime project QSF file. These constraints are designed for the LTC3888 PMIC.
Open your Quartus Prime project QSF file, and copy and paste constraint scripts into
the file. Ensure that there are no other similar settings with different values.
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 62
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
set_global_assignment -name USE_CONF_DONE SDM_IO16
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
6.2. Golden Top
You can use the Golden Top project as the starting point for your designs. It comes
loaded with constraints, pin locations, define I/O standard, direction, and general
termination. The DDR4 pin termination settings are not included. Refer to the DDR4
example designs for details.
776646 | 2024.11.21
Send Feedback
©
Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera
Corporation. Altera and Intel warrant performance of its FPGA and semiconductor products to current
specifications in accordance with Altera’s or Intel's standard warranty as applicable, but reserves the right to
make changes to any products and services at any time without notice. Altera and Intel assume no
responsibility or liability arising out of the application or use of any information, product, or service described
herein except as expressly agreed to inwriting by Altera or Intel. Altera and Intel customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Table of Contents

Related product manuals