User Guide Intel Confidential 3
Contents
1 Introduction .................................................................................................... 9
1.1 Terminology ......................................................................................... 9
1.2 Reference Documents .......................................................................... 10
2 CFL-S RVP Features ....................................................................................... 11
2.1 CFL RVP Block Diagram ........................................................................ 11
2.2 RVP Feature Set Summary .................................................................... 12
3 Key RVP Features and Block Diagrams .............................................................. 14
3.1 DDR4 Memory Topology ....................................................................... 14
3.2 Clock ................................................................................................. 14
3.3 Display Feature on RVP ........................................................................ 15
3.4 PCIe* Mapping .................................................................................... 16
3.5 SATA Interface .................................................................................... 17
3.6 USB 2 Port Mapping ............................................................................. 17
3.7 USB-3 Mapping ................................................................................... 18
3.8 USB Type-C Support ............................................................................ 18
3.9 Audio Feature ..................................................................................... 19
3.10 I2C Mapping ....................................................................................... 19
3.11 GSPI UART and SPI Mapping ................................................................. 20
3.12 SMBUS/SMLINK Mapping ...................................................................... 20
3.13 Connectivity Block ............................................................................... 21
4 RVP Reference Board Summary ....................................................................... 22
5 Power Sources ............................................................................................... 25
5.1 PSU Requirements ............................................................................... 25
6 Hardware Assembly Instructions ...................................................................... 27
6.1 CFL CPU Hardware Assembly Instructions ............................................... 27
6.2 CNP-H Hardware Assembly Instructions .................................................. 29
7 Quick Start Guide .......................................................................................... 34
7.1 Peripherals Required Before Power ON the Board ..................................... 34
7.2 Board Bring-up Steps ........................................................................... 34
7.3 SF600 Programming ............................................................................ 35
7.3.1 SPI through Dediprog SF600 .................................................... 36
7.3.2 Steps for SPI Programming ...................................................... 36
8 Reworks ....................................................................................................... 38
8.1 Mandatory Reworks ............................................................................. 38
8.1.1 Straps to Power On the Board .................................................. 38
8.1.2 Rework to Avoid Leakage from EC to PCH in eSPI Mode ............... 41
8.2 Feature Enabling Reworks .................................................................... 43
8.2.1 Rework to Enable Vertical USB Port ........................................... 43
8.2.2 Rework to Enable TTK Glider Card in eSPI Mode .......................... 46
8.2.3 Rework to Enable CNVi Module ................................................. 50
8.2.4 Rework to Enable PCH XDP ...................................................... 52
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