Intel Coffee Lake S - Rework for Enabling Front Panel USBC Titan Ridge AIC; Figure 42. Layout Snapshot - Top Layer

Reworks
58 Intel Confidential User Guide
Figure 42. Layout Snapshot – Top Layer
8.2.6 Rework for Enabling Front Panel USBC Titan Ridge AIC
Description: CFL-S RVP supports TR SP back panel port and front Panel TR DP AIC.
Only one port is POR at a time. Hence PCIe* lanes and GPIOs are shared between
these ports. This rework is to enable FP TR DP AIC on the RVP that has BP configured
as default.
Impact of implementing the rework:
Default TR SP back panel would be enabled.
After rework FP TR DP AIC would be enabled and BP TR SP will not work.
Details: SMD Resistor/Capacitor rework
Applicable To: H3AZ01, H3AZ02, H4BZ01, H3BZ02.