Intel Coffee Lake S - BIAS Resistor PDG Compliance for 24 Mhz Clock; Figure 79. Schematic Snapshot; Figure 80. Layout Snapshot - Top Layer

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Reworks

User Guide Intel Confidential 89

Figure 79. Schematic Snapshot

Figure 80. Layout Snapshot – Top Layer

8.3.5 BIAS Resistor PDG Compliance for 24MHz Clock

Description: This rework is keep the 24MHz clock’s bias resistor compliant as per

PDG

Impact of implementing the rework:

The current 1MOhm resistor is to be replaced

with 200kohm resistor

Main Page

Table of Contents3
Revision History8
Introduction9
Terminology9
Reference Documents10
CFL-S RVP Features11
CFL RVP Block Diagram11
Figure 1. Coffee Lake S DDR4 RVP Block Diagram (Shown UDIMM Only)11
RVP Feature Set Summary12
Key RVP Features and Block Diagrams14
DDR4 Memory Topology14
Clock14
Figure 2. DDR4 Memory Topology Diagram (Shows Only UDIMM)14
Display Feature on RVP15
Figure 3. Clock15
Pcie* Mapping16
Figure 4. Display Feature Block Diagram16
Figure 5. Pcie* Mapping16
SATA Interface17
USB 2 Port Mapping17
Figure 6. SATA Mapping - Block Diagram17
USB-3 Mapping18
USB Type-C Support18
Figure 7. USB-3 Mapping18
Audio Feature19
I2C Mapping19
Figure 8. Block Diagram - Audio19
GSPI UART and SPI Mapping20
SMBUS/SMLINK Mapping20
Connectivity Block21
Figure 9. Connectivity Block Diagram21
RVP Reference Board Summary22
Figure 10. CFL RVP Reference Board - Top View22
Figure 11. CFL RVP Reference Board - Bottom View23
Figure 12. CFL RVP Reference Board - Front Side View23
Figure 13. CFL RVP Reference Board - Back Panel Side View24
Power Sources25
PSU Requirements25
Hardware Assembly Instructions27
CFL CPU Hardware Assembly Instructions27
CNP-H Hardware Assembly Instructions29
Quick Start Guide34
Peripherals Required before Power on the Board34
Board Bring-Up Steps34
SF600 Programming35
SPI through Dediprog SF60036
Steps for SPI Programming36
Figure 14 SPI through Dediprog SF60036
Figure 15. Load File37
Figure 16. Batch37
Reworks38
Mandatory Reworks38
Straps to Power on the Board38
Table 1. Rework Detail38
Figure 17. Schematic Snapshot39
Figure 18. Schematic Snapshot39
Figure 19. Schematic Snapshot40
Figure 20. Layout Snapshot - Top Layer40
Rework to Avoid Leakage from EC to PCH in Espi Mode41
Figure 21. Layout Snapshot - Bottom41
Figure 22. Schematic Snapshot42
Table 2. Rework Detail42
Feature Enabling Reworks43
Rework to Enable Vertical USB Port43
Figure 23. Layer Snapshot - Top43
Figure 24. Schematic Snapshot44
Table 3. Rework Detail44
Figure 25. Schematic Snapshot45
Rework to Enable TTK Glider Card in Espi Mode46
Figure 26. Layout Snapshot - Top Layer46
Table 4. Rework Detail47
Figure 27. Schematic Snapshot48
Figure 28. Schematic Snapshot48
Figure 29. Layout Snapshot - Top Layer49
Figure 30. Layout Snapshot - Bottom Layer49
Rework to Enable Cnvi Module50
Figure 31. Schematic Snapshot50
Table 5. Rework Detail50
Figure 32. Schematic Snapshot51
Figure 33. Layout Snapshot - Top Layer51
Rework to Enable PCH XDP52
Figure 34. Layout Snapshot - Top Layer52
Table 6. Rework Detail52
Figure 35. Schematic Snapshot53
Figure 36. Schematic Snapshot54
Figure 37. Schematic Snapshot54
Figure 38. Layout Snapshot - Top Layer55
Figure 39. Layout Snapshot - Bottom Layer55
Rework for External Speaker Amplifier in HDA Mode56
Table 7. Rework Detail56
Figure 40. Schematic Snapshot57
Figure 41. Schematic Snapshot57
Rework for Enabling Front Panel USBC Titan Ridge AIC58
Figure 42. Layout Snapshot - Top Layer58
Figure 43. Schematic Snapshot59
Table 8. Rework Detail59
Figure 44. Schematic Snapshot60
Figure 45. Schematic Snapshot60
Figure 46. Layout Snapshot - Top Layer61
Rework for Enabling Back Panel USBC Titan Ridge62
Figure 47. Layout Snapshot - Bottom Layer62
Table 9. Rework Detail63
Figure 48. Schematic Snapshot64
Figure 49. Schematic Snapshot64
Figure 50. Schematic Snapshot65
Figure 51. Layout Snapshot - Top Layer65
Rework to Enable Audio in Soundwire* Mode66
Figure 52. Layout Snapshot - Bottom Layer66
Table 10. Rework Detail66
Figure 53. Schematic Snapshot67
Figure 54. Schematic Snapshot68
Figure 55. Schematic Snapshot69
Rework to Enable Audio HDA Mode on Header70
Figure 56. Layout Snapshot - Top Layer70
Table 11. Rework Detail70
Figure 57. Schematic Snapshot71
Rework to Enable LPC Mode for EC and TPM Header72
Figure 58. Layout Snapshot - Top Layer72
Table 12. Rework Detail72
Figure 59. Schematic Snapshot74
Figure 60. Schematic Snapshot74
Figure 61. Schematic Snapshot75
Figure 62. Schematic Snapshot75
Figure 63. Layout Snapshot - Top Layer76
Figure 64. Layout Snapshot - Bottom Layer77
Figure 65. Layout Snapshot - Top Layer77
Rework to Enable V1P8A Source from PCH Internal LDO to External VR79
Figure 66. Schematic Snapshot79
Table 13. Rework Detail79
Rework to Enable Audio Header for I2S Mode80
Figure 67. Layout Snapshot80
Figure 68. Schematic Snapshot81
Table 14. Rework Detail81
Figure 69. Schematic Snapshot82
Figure 70. Schematic Snapshot82
Optional Reworks83
Rework to Enable Gated CLKREQ for LAN83
Figure 71. Layout Snapshot - Top Layer83
Table 15. Rework Detail83
Figure 72. Schematic Snapshot84
Figure 73. Layout Snapshot - Top Layer84
Rework to Enable Titan Ridge and Pd's Flash85
Figure 74. Schematic Snapshot85
Table 16. Rework Detail85
Rework to Keep USB Compliant on FP Discrete Type C86
Figure 75. Layout Snapshot - Top Layer86
Figure 76. Layout Snapshot - Bottom Layer86
Figure 77. Schematic Snapshot87
Table 17. Rework Detail87
Rework to Enable Debug Consent Strap88
Figure 78. Layout Snapshot - Top Layer88
Table 18. Rework Detail88
BIAS Resistor PDG Compliance for 24Mhz Clock89
Figure 79. Schematic Snapshot89
Figure 80. Layout Snapshot - Top Layer89
Figure 81. Schematic Snapshot90
Table 19. Rework Detail90
Rework to Avoid Leakage on Cnvi and DMIC Modules91
Figure 82. Layout Snapshot - Top Layer91
Table 20. Rework Detail91
AIC Reworks92
Figure 83. Schematic Snapshot92
Figure 84. Layout Snapshot - Top Layer92
Rework to Enable Higher Current Profile on Front Panel USB-C Titan Ridge AIC93
Figure 85. Schematic Snapshot93
Table 21. Rework Detail93
Rework to Enable Sx Wake on Front Panel USB-C Titan Ridge AIC94
Figure 86. Layout Snapshot - Top Layer94
Table 22. Rework Detail94
Rework to Enable RTD3 Flow on Front Panel USBC Titan Ridge AIC95
Figure 87. Schematic Snapshot95
Figure 88. Layout Snapshot - Top Layer95
Figure 89. Schematic Snapshot96
Table 23. Rework Detail96
Figure 90. Layout Snapshot - Bottom Layer97

Intel Coffee Lake S - BIAS Resistor PDG Compliance for 24 Mhz Clock; Figure 79. Schematic Snapshot; Figure 80. Layout Snapshot - Top Layer

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