Intel Coffee Lake S - GSPI UART and SPI Mapping; SMBUS;SMLINK Mapping

Key RVP Features and Block Diagrams
20 Intel Confidential User Guide
ISH I2C Mapping
ISH I2C0(3.3V) Option to onboard sensor
ISH I2C1(3.3V) 1X7 header
ISH I2C2 (muxed with LPSS I2C3)(1.8V) Type-C PD controller, 1X7 header
3.11 GSPI UART and SPI Mapping
LPSS/ISH UART Mapping
LPSS UART0(muxed with CNVi UART BT) M.2 CNVi / UART BT
ISH UART 0 2X3 header
LPSS/ISH UART 1 2X3 header
LPSS UART 2 Serial port and 2 pin header
GSPI Mapping
GSPI0 2X3 header
GSPI1 Fingerprint sensor
GSPI2(muxed with ISH SPI and BSSB
CLK/DATA)
Reserved for BSSB and option for 2X3 header
3.12 SMBUS/SMLINK Mapping
SMBUS and SMLINK
SMBUS
Memory, 1X3 header, Option to PSS, PCIe*
DT Slots, DAC for AVMC, FRU, LPC TPM
header, CPU XDP
SMLINK0(muxed with I2C2 and ISH UART0) LAN, NFC
SMLINK1 EC
SMLINK2 Used as GPIOs
SMLINK3 Used as GPIOs
SMLINK4 Used as GPIOs