10 323094 Dev Kit Manual
port. The Development kit has such a port and it is located on the rear of
the platform between the two USB connectors.
The Intel
®
Mobile Voltage Positioning specification for the Intel
®
Core™ i5
Processor. It is a DC-DC converter module that supplies the required
voltage and current to a single processor.
Inter-Symbol
Interference
Inter-symbol interference is the effect of a previous signal (or transition)
on the interconnect delay. For example, when a signal is transmitted
down a line and the reflections due to the transition have not completely
dissipated, the following data transition launched onto the bus is affected.
ISI is dependent upon frequency, time delay of the line, and the reflection
coefficient at the driver and receiver. ISI may impact both timing and
signal integrity.
This Add-in Card enables Intel
®
High Definition Audio functionality
The network is the trace of a Printed Circuit Board (PCB) that completes
an electrical connection between two or more components.
The maximum voltage observed for a signal at the device pad, measured
with respect to VCC.
The electrical contact point of a semiconductor die to the package
substrate. A pad is only observable in simulations.
The contact point of a component package to the traces on a substrate,
such as the motherboard. Signal quality and timings may be measured at
the pin.
“Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal)
indicates that all of the system power supplies and clocks are stable.
PWRGOOD should go active at a predetermined time after system
voltages are stable and should go inactive as soon as any of these
voltages fail their specifications.
The voltage to which a signal changes after reaching its maximum
absolute value. Ringback may be caused by reflections, driver oscillations,
or other transmission line phenomena.
The System Bus is the microprocessor bus of the processor.
The time between the beginning of Setup to Clock (TSU_MIN) and the
arrival of a valid clock edge. This window may be different for each type
of bus agent in the system.
Simultaneous
Switching Output
Simultaneous Switching Output (SSO) effects are differences in electrical
timing parameters and degradation in signal quality caused by multiple
signal outputs simultaneously switching voltage levels in the opposite
direction from a single signal or in the same direction. These are called
odd mode and even mode switching, respectively. This simultaneous
switching of multiple outputs creates higher current swings that may
cause additional propagation delay (“push-out”) or a decrease in
propagation delay (“pull-in”). These SSO effects may impact the setup
and/or hold times and are not always taken into account by simulations.
System timing budgets should include margin for SSO effects.
The branch from the bus trunk terminating at the pad of an agent.
The main connection, excluding interconnect branches, from one end.
A two-wire interface through which various system components may
communicate.
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