Intel Intel® Core i7 - Table 31. HAD Header for MDC Interposer (J9 E4); Table 32.HAD Header for MDC Interposer (J9 E7)

Dev Kit Manual 57 323094
Pin
Signal
Definition
8
PCH_GPIO24_PWR_EN#
Finger Print Power
Enable
4.6.2.6 HAD Header for MDC Interposer
Table 31. HAD Header for MDC Interposer (J9E4)
Pin
Signal
Definition
1
GND
Ground
2
HDA_MDC_SDATAIN2
Data In 2
3
+V3.3
3.3 volt supply
4
HDA_MDC_SDATAIN23
Data In 3
5
N/C
Reserved
6
HDA_MDC_SDATAIN21
Data In 1
7
VBATS_HDA_R1
6V – 14.1V supply
8
HDA_MDC_SDATAIN20
Data In 0
9
+V3.3
3.3 volt supply
10
HDA_MDC_SDO
Data Out
11
GND
Ground
12
HDA_MDC_SYNC
Synch
13
V3.3A_1.5A_HDA_IO
3.3 volt supply
14
HDA_MDC_RST#
Reset
15
GND
Ground
16
HDA_MDC_BITCLK
Clock
Table 32.HAD Header for MDC Interposer (J9E7)
Pin
Signal
Definition
1
HDA_AUDIO_PWRDN_NET
Pull-down to low
2
HDA_SPKR_R
Speaker
3
GND
Ground
4
+V5
5 volt supply
5
+V3.3A
3.3 volt supply
6
MEMS_CLK_R
Clock
7
HDA_DOCK_RST#_R
Reset (active low)
8
HDA_DOCK_EN#_R
Dock enable