148 E8257D/67D, E8663D PSG Signal Generators Service Guide
Troubleshooting
Reference/Synthesis Loop Description
The phase detector error voltage is integrated and summed with the YIG
oscillator pre–tune voltage on the A9 YIG Driver, fine tuning the YIG oscillator
output to exactly 5 GHz.
Ramp Sweep
(Option 007)
The following basic functions are required to generate an accurate sweep in
ramp sweep mode:
—coarse and fine tune
—sweep rate control
—sweep generation
— output frequency monitoring or feedback
Example (start 3.2 GHz, stop 10 GHz, sweep rate 50 ms)
The A18 CPU sets the A9 YIG Driver Sweep DAC for a +3.2V output, which
results in a YIG oscillator output of approximately 3.2 GHz. To sweep the
instrument from 3.2 to 10 GHz, a programmable counter on the A9 YIG Driver
increments the Sweep DAC’s output to +10V.
The speed at which the output of the Sweep DAC changes determines the
instrument's sweep rate. The rate of change is controlled by the output
frequency of a digitally developed synthesis (DDS) chip on the A9 YIG Driver.
The A18 CPU sets the DDS output to a frequency between 0 and 25 MHz, and
the DDS output frequency clocks a programmable counter that drives the
Sweep DAC rate of change. A low DDS frequency produces a slow sweep rate;
a high DDS frequency produces a high sweep rate.
In ramp sweep mode, the A9 YIG Driver Pre–tune DAC is set to 0V. Delay
compensation is added to improve linearity, and a fine tune correction from the
A6 Frac–N is summed with the Sweep DAC voltage to maintain phase lock. The
phase lock correction voltage is generated on the A6 Frac–N by coupling off
some of the YIG output frequency in the A29 20 GHz Doubler, and routing it to
the A6 Frac–N. On the A6 Frac–N, fixed and programmable dividers (controlled
by the A18 CPU) divide the RF signal down to 5 MHz.
Also on the A6 Frac–N, 10 MHz from the A7 Reference is divided down to
5 MHz. The phase of the two 5 MHz signals is compared and integrated. The
integrator’s output is routed to the A9 YIG Driver and summed with the Sweep
DAC (YIG Drive) voltage to maintain phase lock during sweep.
After the A18 CPU has everything set up, the A9 YIG Driver programmable
counter is enabled and sweep begins. The A6 Frac–N divide numbers
determine how far the A6 Frac–N sweeps before the A18 CPU calculates new
divide numbers. The A6 Frac–N divide numbers are updated at filter switch
points and at band crossings. During multiple band sweeps, the A9 YIG Driver
Sweep DAC, DDS, and delay compensation are updated at band crossings.
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