PQIII Debugger | 20
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Debugging Information
In order to properly use all debug features (breakpoints, single step etc) of the MPC85XX, the Debug
Interrupt Vector (IVPR+IVOR15) must be set to an address which is
• properly mapped in the MMU (memory management unit) and
• points to an address which contains a valid instruction (NOP is recommended).
Please note that both IVOR/IVPR and memory contents can be changed by the application any time,
especially during the boot process. When debugging is done after the boot process finished, the interrupt
vector and memory is usually properly set up by the application. There are however operating systems that
don’t use the debug interrupt and let it point to an illegal instruction.
For early CPU revisions (PVR=0x8020XXXX) it is recommended to place the instructions NOP followed by
RFCI to the debug interrupt vector. These two instructions are needed for SYStem.Option.FREEZE.
Multicore Debugging e500 cores
SMP Debugging
For the dual-core processors MPC8572 and the dual-core variants of P10xx and P20xx, SMP debugging is
selected by default. No further configuration is needed. As soon as the debugger is connected (SYStem.Up,
SYStem.Mode.Attach etc.), it is possible to switch to any core using the CORE <core_index> command.
The currently selected core is displayed in the status line. If the cores are running and one of the cores hits a
breakpoint, the debugger’s view will automatically switch to this core.
; CORE 1 setup script: ; CORE 2 setup script:
SYStem.CPU 5516 SYStem.CPU 5516
SYStem.CONFIG.CORE 1. 1. SYStem.CONFIG.CORE 2. 1.
SYStem.UP SYStem.Mode.Attach
; do board initialization here ; z0 is still in reset
Data.LOAD.Elf demo.elf Data.LOAD.Elf demo.elf /NoCODE
Break ; with this command
; z0 will stop when
; reset is released
Go ; start z1
; application will start z0
; core
WAIT !RUN() ; wait until cpu stops
Break.Set somez0function
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