Lauterbach TRACE32-ICD - User Manual

MANUAL
Release 02.2022
PPC600 Family Debugger

Lauterbach TRACE32-ICD Specifications

General

Manufacturer	Lauterbach
Model	TRACE32-ICD
Operating System Support	Windows, Linux
Category	Computer Accessories
Type	In-Circuit Debugger
Supported Architectures	ARM, Power Architecture, x86
Interface	JTAG, SWD, Nexus
Power Supply	External power supply
Software	TRACE32 software suite
Debugging Features	breakpoints, watchpoints, memory access
Trace Features	Instruction trace, data trace

Summary

Warnings and Safety Precautions

Signal Level Considerations

ESD Protection Guidelines

Provides steps for connecting/disconnecting the debug cable to prevent ESD damage.

Target Design Requirements and Recommendations

General Design Recommendations

Quick Start Guide

Troubleshooting Debugging Issues

Handling Memory Access Issues

System Configuration

System Overview Diagram

Illustrates the setup with SWITCH, PC/Workstation, Debug Cable, and Target.

PowerPC 600 Family Specific Implementations

Breakpoints in PowerPC Debugging

Covers software and on-chip breakpoints, including their usage and limitations.

Software Breakpoint Handling Logic

On-chip Breakpoint Capabilities

Software Breakpoints in Interrupt Handlers

Breakpoints in FLASH;ROM

Breakpoints on Physical vs. Virtual Addresses

Breakpoint Examples

CPU Specific System Commands

System.BdmClock: Set JTAG Frequency

Configures the JTAG frequency for the debug interface.

System.CPU: Select CPU Type

System.LOCK: Lock Debug Port

System.MemAccess: Real-time Memory Access

System.Mode: Select Operation Mode

System.CONFIG.state: Display Target Configuration

System.CONFIG: Configure Debugger Topology

JTAG Daisy-Chain Example

System.CONFIG.CORE: Assign Core to TRACE32 Instance

System.Option.BASE: Set Peripheral Base Address

System.Option.BUS32: Use 32-Bit Data-Bus Mode

System.Option.CONFIG: Select RCW Configuration

System.Option.DUALPORT: Implicit Run-time Memory Access

System.Option.HoldReset: Set Reset Hold Time

System.Option.HRCWOVerRide: Override HRCW on System.Up

System.Option.ICFLUSH: Invalidate Instruction Cache

System.Option.IMASKASM: Disable Interrupts During ASM Step

System.Option.IMASKHLL: Disable Interrupts During HLL Step

System.Option.IP: Set MSR_IP for Breakpoints

System.Option.LittleEnd: True Little Endian Mode

System.Option.MemProtect: Enable Memory Access Safeguard

System.Option.MMUSPACES: Separate Address Spaces

System.Option.NoDebugStop: Disable JTAG Stop on Debug Events

System.Option.NOTRAP: Alternative Software Breakpoint Instruction

System.Option.OVERLAY: Enable Overlay Support

System.Option.PINTDebug: Program Interrupt Debugging

System.Option.PPCLittleEnd: PPC Little Endian Mode

System.Option.RESetBehavior: Set Target Reset Behavior

System.Option.ResetMode: Select System.Up Reset Method

System.Option.SLOWRESET: Relaxed Reset Timing

System.Option.STEPSOFT: Alternative ASM Single Step

System.Option.WaitReset: Set Reset Wait Time

System.Option.WATCHDOG: Leave Software Watchdog Enabled

CPU Specific MMU Commands

MMU.DUMP: Page Wise MMU Translation Table Display

MMU.List: Compact MMU Translation Table Display

MMU.SCAN: Load MMU Table from CPU

MMU.Set: Write MMU TLB Entries to CPU

CPU Specific BenchMarkCounter Commands

BMC.<counter>.FREEZE: Freeze Counter in Specific Core States

BMC.FREEZE: Freeze Counters While Core Halted

CPU Specific TrOnchip Commands

TrOnchip.CONVert: Adjust Range Breakpoint

TrOnchip.VarCONVert: Adjust Complex Breakpoint

Mechanical Description of JTAG;COP Connector

JTAG;COP Connector Pinout (PPC603 e;700;MPC8200)