Name: Lauterbach TRACE32-ICD
Brand: Lauterbach
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PPC600 Family Debugger | 38

1989-2022 Lauterbach

SYStem.Option.FREEZE Freeze timebase when core halted

When enabled, the core’s timebase is stopped when the core is halted in debug mode. It is recommended to

set this option ON.

Format: SYStem.Option.FREEZE [ON | OFF]

PPC600 Family Debugger1
Table of Contents2
Introduction6
Brief Overview of Documents for New Users6
Warning7
Signal Level7
ESD Protection7
Target Design Requirement/Recommendations8
General8
Quick Start9
Troubleshooting11
Problems with Memory Access12
Faq12
Configuration13
System Overview13
Powerpc 600 Family Specific Implementations14
Breakpoints14
Software Breakpoints14
Software Breakpoint Handling15
On-Chip Breakpoints17
Software Breakpoints in Interrupt Handlers18
Breakpoints in FLASH/ROM18
Breakpoints on Physical or Virtual Addresses18
Examples for Breakpoints19
Software Breakpoints19
On-Chip Program Address Breakpoints19
On-Chip Data Address Breakpoints19
Access Classes20
Access Classes to Memory and Memory Mapped Resources20
Access Classes to Other Addressable Core and Peripheral Resources21
Cache21
Memory Coherency21
MESI States22
Little Endian Operation23
CPU Specific System Commands24
System.bdmclock24
Set JTAG Frequency24
System.cpu24
Select the CPU Type24
System.lock25
Lock and Tristate the Debug Port25
System.memaccess25
Real-Time Memory Access (Non-Intrusive)25
System.mode26
Select Operation Mode26
System.config.state27
Display Target Configuration27
System.config28
Configure Debugger According to Target Topology28
Daisy-Chain Example31
Tapstates32
System.config.chkstpin Control Pin 8 of Debug Connector32
System.config.core Assign Core to TRACE32 Instance33
System.config.driverstrength34
Configure Driver Strength of TCK Pin34
System.config.qack34
Control QACK Pin34
CPU Specific System Commands35
System.option.base35
Set Base Address for On-Chip Peripherals35
System.option.bus3236
Use 32-Bit Data-Bus Mode36
System.option.config36
Select RCW Configuration36
System.option.dcread37
Read from Data Cache37
System.option.dualport37
Implicitly Use Run-Time Memory Access37
System.option.freeze Freeze Timebase When Core Halted38
System.option.holdreset39
Set Reset Hold Time39
System.option.hook39
Compare PC to Hook Address39
System.option.hrcwoverride40
Override HRCW on System.up40
System.option.icflush40
Invalidate Instruction Cache before Go/Step40
System.option.icread41
Read from Instruction Cache41
System.option.imaskasm41
Disable Interrupts While Single Stepping41
System.option.imaskhll41
Disable Interrupts While HLL Single Stepping41
System.option.ip42
Set MSR_IP Value for Breakpoints / System.up42
System.option.littleend42
True Little Endian Mode42
System.option.memprotect42
Enable Memory Access Safeguard42
System.option.memspeed43
Configure Memory Access Timing43
System.option.mmuspaces43
Separate Address Spaces by Space Ids43
System.option.nodebugstop44
Disable JTAG Stop on Debug Events44
System.option.notrap45
Use Alternative Software Breakpoint Instruction45
System.option.overlay46
Enable Overlay Support46
System.option.parity46
Generate Parity on Memory Access46
System.option.pintdebug47
Program Interrupt Debugging47
System.option.ppclittleend47
PPC Little Endian Mode47
System.option.pte48
Evaluate PTE Table for Address Translation48
System.option.resetbehavior48
Set Behavior When Target Reset Detected48
System.option.resetmode49
Select Reset Mode for System.up49
System.option.slowreset49
Relaxed Reset Timing49
System.option.stepsoft50
Use Alternative Method for ASM Single Step50
System.option.waitreset51
Set Reset Wait Time51
System.option.watchdog52
Leave Software Watchdog Enabled52
CPU Specific MMU Commands53
Mmu.dump53
Page Wise Display of MMU Translation Table53
Mmu.list55
Compact Display of MMU Translation Table55
Mmu.scan57
Load MMU Table from CPU57
Mmu.set58
Write MMU TLB Entries to CPU58
CPU Specific Benchmarkcounter Commands59
Bmc.<Counter>.Freeze59
Freeze Counter in Certain Core States59
BMC.FREEZE Freeze Counters While Core Halted60
CPU Specific Tronchip Commands61
Tronchip.disable61
Disable Debug Register Control61
Tronchip.enable61
Enable Debug Register Control61
Tronchip.convert61
Adjust Range Breakpoint in On-Chip Resource61
Tronchip.varconvert62
Adjust Complex Breakpoint in On-Chip Resource62
Tronchip.reset62
Reset On-Chip Trigger Settings62
Tronchip.state62
Display On-Chip Trigger Window62
Tronchip.tenable62
Set Filter for the Trace62
Tronchip.toff63
Switch the Sampling to the Trace to off63
Tronchip.ton63
Switch the Sampling to the Trace to "ON63
Tronchip.ttrigger63
Set a Trigger for the Trace63
Mechanical Description64
JTAG/COP Connector Ppc603E/700/Mpc820064
Technical Data65

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General

Brand	Lauterbach
Model	TRACE32-ICD
Category	Computer Accessories
Language	English

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Table of Contents

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