PPC600 Family Debugger | 41
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SYStem.Option.ICREAD Read from instruction cache
Data.List window and Data.dump window for access class P: displays the memory value from the
instruction cache if valid. If I-cache is not valid the physical memory will be read. If supported by the CPU,
L2 caches will also be used if this system option is enabled.
SYStem.Option.IMASKASM Disable interrupts while single stepping
Default: OFF. If enabled, the interrupt mask bits of the CPU will be set during assembler single-step
operations. The interrupt routine is not executed during single-step operations. After single step the interrupt
mask bits are restored to the value before the step.
SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping
Default: OFF. If enabled, the interrupt mask bits of the cpu will be set during HLL single-step operations. The
interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are
restored to the value before the step.
NOTE: Don’t enable this option for code that disables MSR_EE. The debugger will disable MSR_EE while
the CPU is running and restore it after the CPU stopped. If a part of the application is executed that disables
MSE_EE, the debugger can not detect this change and will restore MSE_EE.
Format: SYStem.Option.ICREAD [ON | OFF]
Format: SYStem.Option.IMASKASM [ON | OFF]
Format: SYStem.Option.IMASKHLL [ON | OFF]
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